Hitachi H8/3048 Hardware Manual page 7

8.3.2 I/O Address Registers (IOAR)........................................................................ 196
8.3.3 Execute Transfer Count Registers (ETCR)..................................................... 197
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8.3.4 Data Transfer Control Registers (DTCR) ....................................................... 199
8.4 Operation ........................................................................................................................ 205
8.4.1 Overview......................................................................................................... 205
8.4.2 I/O Mode......................................................................................................... 207
8.4.3 Idle Mode........................................................................................................ 209
8.4.4 Repeat Mode................................................................................................... 212
8.4.5 Normal Mode.................................................................................................. 215
8.4.6 Block Transfer Mode ...................................................................................... 218
8.4.7 DMAC Activation........................................................................................... 223
8.4.8 DMAC Bus Cycle ........................................................................................... 225
8.4.9 Multiple-Channel Operation........................................................................... 231
8.4.10 External Bus Requests, Refresh Controller, and DMAC................................ 232
8.4.11 NMI Interrupts and DMAC ............................................................................ 233
8.4.12 Aborting a DMA Transfer .............................................................................. 234
8.4.13 Exiting Full Address Mode............................................................................. 235
8.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode .................... 236
8.5 Interrupts......................................................................................................................... 237
8.6 Usage Notes .................................................................................................................... 238
8.6.1 Note on Word Data Transfer........................................................................... 238
8.6.2 DMAC Self-Access ........................................................................................ 238
8.6.3 Longword Access to Memory Address Registers........................................... 238
8.6.4 Note on Full Address Mode Setup.................................................................. 238
8.6.5 Note on Activating DMAC by Internal Interrupts .......................................... 239
8.6.6 NMI Interrupts and Block Transfer Mode ...................................................... 240
8.6.7 Memory and I/O Address Register Values ..................................................... 240
8.6.8 Bus Cycle when Transfer is Aborted .............................................................. 241
Section 9 I/O Ports
9.1 Overview......................................................................................................................... 243
9.2 Port 1............................................................................................................................... 246
9.2.1 Overview......................................................................................................... 246
9.2.2 Register Descriptions...................................................................................... 247
9.3 Port 2............................................................................................................................... 249
9.3.1 Overview......................................................................................................... 249
9.3.2 Register Descriptions...................................................................................... 250
9.4 Port 3............................................................................................................................... 253
9.4.1 Overview......................................................................................................... 253
9.4.2 Register Descriptions...................................................................................... 253
9.5 Port 4............................................................................................................................... 255
....................................................................................................... 243