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8.1.2 Block Diagram
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Figure 8-1 shows a DMAC block diagram.
Internal
IMIA0
interrupts
IMIA1
IMIA2
IMIA3
TXI0
RXI0
DREQ0
DREQ1
TEND0
TEND1
Interrupt
DEND0A
signals
DEND0B
DEND1A
DEND1B
Data buffer
Legend
DTCR:
Data transfer control register
MAR:
Memory address register
IOAR:
I/O address register
ETCR:
Execute transfer count register
Internal address bus
Channel
Control logic
0
DTCR0A
DTCR0B
DTCR1A
DTCR1B
Channel
1
Internal data bus
Figure 8-1 Block Diagram of DMAC
186
Address buffer
Arithmetic-logic unit
MAR0A
Channel
IOAR0A
0A
ETCR0A
MAR0B
Channel
IOAR0B
0B
ETCR0B
MAR1A
Channel
IOAR1A
1A
ETCR1A
MAR1B
Channel
IOAR1B
1B
ETCR1B
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