Clearing Of Status Flags - Hitachi H8/3048 Hardware Manual

Single-chip microcomputer
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ø
TCNT
H'FFFF
Overflow
signal
OVF
OVI

10.5.2 Clearing of Status Flags

If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is
cleared. Figure 10-60 shows the timing.
ø
Address
IMF, OVF
Figure 10-60 Timing of Clearing of Status Flags
Figure 10-59 Timing of Setting of OVF
TSR write cycle
T
1
378
H'0000
T
T
2
3
TSR address

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