Hitachi H8/3048 Hardware Manual page 707

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A to A
9 1
AS
CS (RAS)
3
HWR (UCAS),
LWR (LCAS)
RD (WE)
RFSH
Figure 21-14 DRAM Bus Timing (Refresh Cycle): Three-State Access
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CS (RAS)
3
HWR UCAS
( ),
LWR LCAS)
(
RFSH
T
1
t
ASD
t
CSR
t t
ASD RAD2
t
RAD2
t
CSR
— 2CAS Mode —
t
CSR
t
CSR
Figure 21-15 DRAM Bus Timing (Self-Refresh Mode)
— 2CAS Mode —
T T
2 3
t
SD
t
RAD3
t
SD
t
RAD3
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