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Example 4: Connection to Multiple 4-Mbit DRAM Chips (16-Mbyte Mode): Figure 7-13
shows an example of interconnections to two 2CAS 4-Mbit DRAM chips, and the corresponding
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address map. Up to four DRAM chips can be connected to area 3 by decoding upper address bits
A
and A
.
19
20
Figure 7-14 shows a setup procedure to be followed by a program for this example. The DRAM
in this example has 9-bit row addresses and 9-bit column addresses. Both chips must be refreshed
simultaneously, so the RFSH pin must be used.
H8/3048 Series
A to A
D
H'600000
H'67FFFF
H'680000
H'6FFFFF
H'700000
H'7FFFFF
Figure 7-13 Interconnections and Address Map for Multiple 2CAS 4-Mbit DRAM Chips
A
19
9
1
CS
3
HWR
LWR
RD
RFSH
to D
15
0
a. Interconnections (example)
No. 1
DRAM area
No. 2
DRAM area
Area 3 (16-Mbyte mode)
Not used
b. Address map
(Example)
170
CAS
2
4-Mbit DRAM with 9-bit
row address, 9-bit column
×
address, and
16-bit organization
A to A
8
0
RAS
UCAS
No. 1
LCAS
WE
OE
I/O
to I/O
15
0
A to A
8
0
RAS
UCAS
LCAS
No. 2
WE
OE
I/O
to I/O
15
0
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