Hitachi H8/3048 Hardware Manual page 18

Single-chip microcomputer
Table of Contents

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Table 1-1 Features (cont)
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Feature
Description
Refresh
DRAM refresh
controller
• Directly connectable to 16-bit-wide DRAM
• CAS-before-RAS refresh
• Self-refresh mode selectable
Pseudo-static RAM refresh
• Self-refresh mode selectable
Usable as an interval timer
DMA controller
Short address mode
(DMAC)
• Maximum four channels available
• Selection of I/O mode, idle mode, or repeat mode
• Can be activated by compare match/input capture A interrupts from ITU
Full address mode
• Maximum two channels available
• Selection of normal mode or block transfer mode
• Can be activated by compare match/input capture A interrupts from ITU
16-bit integrated
• Five 16-bit timer channels, capable of processing up to 12 pulse outputs or 10
timer unit (ITU)
• 16-bit timer counter (channels 0 to 4)
• Two multiplexed output compare/input capture pins (channels 0 to 4)
• Operation can be synchronized (channels 0 to 4)
• PWM mode available (channels 0 to 4)
• Phase counting mode available (channel 2)
• Buffering available (channels 3 and 4)
• Reset-synchronized PWM mode available (channels 3 and 4)
• Complementary PWM mode available (channels 3 and 4)
• DMAC can be activated by compare match/input capture A interrupts
Programmable
• Maximum 16-bit pulse output, using ITU as time base
timing pattern
• Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups)
controller (TPC)
• Non-overlap mode available
• Output data can be transferred by DMAC
Watchdog
• Reset signal can be generated by overflow
timer (WDT),
• Reset signal can be output externally
1 channel
• Usable as an interval timer
Serial
• Selection of asynchronous or synchronous mode
communication
• Full duplex: can transmit and receive simultaneously
interface (SCI),
• On-chip baud-rate generator
2 channels
• Smart card interface functions added (SCI0 only)
channels 0 to 3, transmit-data-empty and receive-data-full interrupts from SCI
channel 0, or external requests
channels 0 to 3, external requests, or auto-request
pulse inputs
(channels 0 to 3)
3

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