Hitachi H8/3048 Hardware Manual page 328

Bit 5—Master Enable TOCXB4 (EXB4): Enables or disables ITU output at pin TOCXB
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Bit 5
EXB4 Description
0 TOCXB output is disabled regardless of TFCR settings (TOCXB
4
input/output pin).
If XTGD = 0, EXB4 is cleared to 0 when input capture A occurs in channel 1.
1 TOCXB is enabled for output according to TFCR settings
4
Bit 4—Master Enable TOCXA4 (EXA4): Enables or disables ITU output at pin TOCXA
Bit 4
EXA4 Description
0 TOCXA output is disabled regardless of TFCR settings (TOCXA
4
input/output pin).
If XTGD = 0, EXA4 is cleared to 0 when input capture A occurs in channel 1.
1 TOCXA is enabled for output according to TFCR settings
4
Bit 3—Master Enable TIOCB3 (EB3): Enables or disables ITU output at pin TIOCB
Bit 3
EB3 Description
0 TIOCB output is disabled regardless of TIOR3 and TFCR settings (TIOCB
3
a generic input/output pin).
If XTGD = 0, EB3 is cleared to 0 when input capture A occurs in channel 1.
1 TIOCB is enabled for output according to TIOR3 and TFCR settings
3
316
.
4
operates as a generic
4
(Initial value)
.
4
operates as a generic
4
(Initial value)
.
3
operates as
3
(Initial value)