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ø
Address bus
CS
n
AS
RD
Read
D
to D
15
access
D to D
7
0
HWR
LWR
Write
access
D
to D
15
D to D
7
0
Note: n = 7 to 0
Figure 6-8 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3)
T
1
8
8
(Word Access)
Bus cycle
T
2
External address in area n
Valid
Valid
129
T
3
Valid
Valid
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