Hitachi H8/3048 Hardware Manual page 858

Table D-1 Port States (cont)
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Pin
Name Mode
P8 to P8 1 to 6
3 1
7
P8 1 to 6
4
7
P9 to P9 1 to 7
6 0
PA to PA 1 to 7
3 0
PA to PA 3, 4, 6
6 4
1, 2, 5, 7
PA 3, 4, 6
7
1, 2, 5, 7
PB , PB to 1 to 7
7 5
PB
0
PB 3, 4, 6
6
1, 2, 5, 7
Legend
H: High
L: Low
T: High-impedance state
keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register bit
Notes: 1. The bus cannot be released in mode 7.
2. Output is low only for reset by WDT overflow.
3. During direct power supply, oscillation damping time is "H" or "T".
4. During direct power supply, oscillation damping time differs between "H", "L" and "T".
Hardware Software
Standby
Reset Mode
T T
T T
L T
T T
T T
T T
4
T* T
4
T* T
4
L* T
T T
T T
T T
T T
851
Bus-
Standby Released
Mode Mode
T keep
(DDR = 0) (DDR = 0)
H H
(DDR = 1) (DDR = 1)
keep —
T keep
(DDR = 0) (DDR = 0)
L H
(DDR = 1) (DDR = 1)
keep —
1
keep keep*
1
keep keep*
H H
(CS output) (CS output) (CS output)
T (address T (address A23 to A21
output) output)
keep keep
(otherwise) (otherwise) I/O port
1
keep keep*
T T
1
keep keep*
1
keep keep*
H H
(CS output) (CS output) (CS output)
keep keep
(otherwise) (otherwise) (otherwise)
1
keep keep*
Program
Execution,
Sleep Mode
Input port
(DDR = 0) or
CS to CS
3 1
(DDR = 1)
I/O port
Input port
(DDR = 0)
or CS
0
(DDR = 1)
I/O port
I/O port
I/O port
CS6 to CS4
(address
output)
(otherwise)
I/O port
A
20
I/O port
I/O port
CS7
I/O port
I/O port