Hitachi H8/3048 Hardware Manual page 209

Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND)
requested when the DTE bit is cleared to 0.
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Bit 3
DTIE Description
0 The DEND interrupt requested by DTE is disabled
1 The DEND interrupt requested by DTE is enabled
Bits 2 to 0—Data Transfer Select (DTS2, DTS1, DTS0): These bits select the data transfer
activation source. Some of the selectable sources differ between channels A and B.*
Note: * Refer to 8-3-4, Data Transfer Control Registers (DTCR).
Bit 2 Bit 1
DTS2 DTS1
0 0
1
1 0
1
The same internal interrupt can be selected as an activation source for two or more channels at
once. In that case the channels are activated in a priority order, highest-priority channel first. For
the priority order, see section 8.4.9, Multiple-Channel Operation.
When a channel is enabled (DTE = 1), its selected DMAC activation source cannot generate a
CPU interrupt.
Bit 0
DTS0 Description
0 Compare match/input capture A interrupt from ITU
channel 0
1 Compare match/input capture A interrupt from ITU channel 1
0 Compare match/input capture A interrupt from ITU channel 2
1 Compare match/input capture A interrupt from ITU channel 3
0 Transmit-data-empty interrupt from SCI channel 0
1 Receive-data-full interrupt from SCI channel 0
0 Falling edge of
Transfer in full address mode (channel A)
Low level of DREQ input (channel B)
1
Transfer in full address mode (channel A)
DREQ input (channel B)
195
(Initial value)
(Initial value)