Hitachi H8/3048 Hardware Manual page 777

TCR0—Timer Control Register 0
www.DataSheet4U.com
Bit 7
—
Initial value 1
Read/Write —
Counter clear 1 and 0
Bit 6
CCLR1 CCLR0
6 5
CCLR1 CCLR0 CKEG1
0 0
R/W R/W
Timer prescaler 2 to 0
Bit 2 Bit 1
TPSC2 TPSC1 TPSC0
0 0
1
1 0
1
Clock edge 1 and 0
Bit 4
Bit 3
CKEG1 CKEG0 Counted Edges of External Clock
0 0 Rising edges counted
1 Falling edges counted
1 — Both edges counted
Bit 5
TCNT Clear Source
0 0 TCNT is not cleared
1 TCNT is cleared by GRA compare match or input capture
1 0 TCNT is cleared by GRB compare match or input capture
1 Synchronous clear: TCNT is cleared in synchronization
with other synchronized timers
770
H'64
4 3 2
CKEG0 TPSC2
0 0 0
R/W R/W R/W
Bit 0
TCNT Clock Source
0 Internal clock: ø
1 Internal clock: ø/2
0 Internal clock: ø/4
1 Internal clock: ø/8
0 External clock A: TCLKA input
1 External clock B: TCLKB input
0 External clock C: TCLKC input
1 External clock D: TCLKD input
ITU0
1 0
TPSC1 TPSC0
0 0
R/W R/W