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18.5.2 Erase Block Register 1
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Erase block register 1 (EBR1) is an eight-bit register that designates large flash-memory blocks
for programming and erasure. EBR1 is initialized to H'00 by a reset, in the standby modes, when
12 V is applied to V
in EBR1 is set to 1, the corresponding block is selected and can be programmed and erased.
Figure 18-8 shows a block map.
Bit
7
LB7
*
Initial value
0
R/W *
R/W
Note: * The initial value is H'00 in modes 5, 6, and 7 (on-chip flash memory enabled). In modes
1, 2, 3, and 4 (on-chip flash memory disabled), this register cannot be modified and is
always read as H'FF.
Bits 7 to 0—Large Block 7 to 0 (LB7 to LB0): These bits select large blocks (LB7 to LB0) to be
programmed and erased.
Bits 7 to 0
LB7 to LB0
0
1
while the V
E bit is 0, and when 12 V is not applied to V
PP
PP
6
5
LB6
LB5
LB4
0
0
*
*
R/W
R/W
R/W
Description
Block LB7 to LB0 is not selected
Block LB7 to LB0 is selected
4
3
2
LB3
LB2
0
0
0
*
*
*
R/W
R/W
577
. When a bit
PP
1
0
LB1
LB0
0
0
*
*
R/W
R/W
(Initial value)
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