Hitachi H8/3048 Hardware Manual page 482

Single-chip microcomputer
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In transmitting serial data, the SCI operates as follows.
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The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
After loading the data from TDR into TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
— Start bit:
— Transmit data:
— Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor
— Stop bit:
— Mark state:
The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of
the next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the
stop bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a
transmit-end interrupt (TEI) is requested at this time.
Figure 13-6 shows an example of SCI transmit operation in asynchronous mode.
Start
1
bit
TDRE
TEND
TXI
interrupt
request
Figure 13-6 Example of SCI Transmit Operation in Asynchronous Mode
One 0 bit is output.
7 or 8 bits are output, LSB first.
bit is output. Formats in which neither a parity bit nor a
multiprocessor bit is output can also be selected.
One or two 1 bits (stop bits) are output.
Output of 1 bits continues until the start bit of the next
transmit data.
Parity
Data
bit
0
D0
D1
D7
0/1
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
1 frame
(8-Bit Data with Parity and 1 Stop Bit)
Stop
Start
Data
bit
bit
1
0
D0
D1
TXI
interrupt
request
471
Parity
Stop
1
bit
bit
D7
0/1
1
Idle (mark)
state
TEI interrupt request

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