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Table A-3 Number of States per Cycle
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Cycle
Instruction fetch
S
Branch address read
S
Stack operation
S
Byte data access
S
Word data access
S
Internal operation
S
Legend
m: Number of wait states inserted into external device access
On-Chip Sup-
porting Module
On-Chip
8-Bit
Memory
Bus
2
6
I
J
K
3
L
6
M
1
N
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Access Conditions
External Device
8-Bit Bus
16-Bit
2-State
3-State
Bus
Access Access Access Access
3
4
6 + 2m
2
3 + m
4
6 + 2m
16-Bit Bus
2-State
3-State
2
3 + m
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