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16-Bit, Two-State-Access Areas: Figures 6-9 to 6-11 show the timing of bus control signals for a
16-bit, two-state-access area. In these areas, the upper address bus (D
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even addresses and the lower address bus (D
cannot be inserted.
ø
Address bus
CS
n
AS
RD
Read
D
15
access
D to D
7
HWR
LWR
Write
access
D
15
D to D
7
Note: n = 7 to 0
Figure 6-9 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1)
to D
7
T
1
Even external address in area n
to D
8
0
High
to D
8
0
(Byte Access to Even Address)
130
to D
15
) is used to access odd addresses. Wait states
0
Bus cycle
T
2
Valid
Invalid
Valid
Undetermined data
) is used to access
8
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