Table of Contents
Advertisement
www.DataSheet4U.com
t
ø
AD
A
to A
23
0
AS
CS
3
t
AS1
RD (read)
D
to D
15
0
(read)
HWR, LWR
(write)
D
to D
15
0
(write)
RFSH
Figure 21-16 PSRAM Bus Timing (Read/Write): Three-State Access
T
ø
A
to A
23
0
AS
, HWR,
CS
3
LWR, RD
RFSH
Figure 21-17 PSRAM Bus Timing (Refresh Cycle): Three-State Access
T
T
1
2
t
RAD1
t
RSD
t
WSD
t
WDS2
T
1
2
t
RAD2
700
T
3
t
RAD3
t
RP
t
SD
t
t
RDS
RDH
t
SD
T
3
t
RAD3
Advertisement
Table of Contents
