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16-Bit, Three-State-Access Areas: Figures 6-6 to 6-8 show the timing of bus control signals for a
16-bit, three-state-access area. In these areas, the upper address bus (D
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even addresses and the lower address bus (D
can be inserted.
ø
Address bus
CS
n
AS
RD
Read
D
to D
15
access
D to D
7
HWR
LWR
Write
access
D
to D
15
D to D
7
Note: n = 7 to 0
Figure 6-6 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1)
T
1
8
0
High
8
0
(Byte Access to Even Address)
to D
) is used to access odd addresses. Wait states
7
0
Bus cycle
T
2
Even external address in area n
Valid
Undetermined data
127
to D
) is used to access
15
8
T
3
Valid
Invalid
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