Hitachi H8/3048 Hardware Manual page 438

Bit 7—Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed
from H'FF to H'00.
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Bit 7
OVF Description
0 [Clearing condition]
Cleared by reading OVF when OVF = 1, then writing 0 in OVF
1 [Setting condition]
Set when TCNT changes from H'FF to H'00
Bit 6—Timer Mode Select
interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request
when TCNT overflows. If used as a watchdog timer, the WDT generates a reset signal when
TCNT overflows.
Bit 6
WT/IT Description
0 Interval timer: requests interval timer interrupts
1 Watchdog timer: generates a reset signal
Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.
When WT/IT = 1, clear the SYSCR software standby bit (SSBY) to 0, then set the TME to 1.
When SSBY is set to 1, clear TME to 0.
Bit 5
TME Description
0 TCNT is initialized to H'00 and halted
1 TCNT is counting and CPU interrupt requests are enabled
Bits 4 and 3—Reserved: Read-only bits, always read as 1.
(WT/IT): Selects whether to use the WDT as a watchdog timer or
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