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17.3 Operation
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When the RAME bit is set to 1, the on-chip RAM is enabled. Accesses to addresses H'FEF10 to
H'FFF0F in the H8/3048 and H8/3047 in modes 1, 2, 5, and 7, addresses H'FFEF10 to H'FFFF0F
in the H8/3048 and H8/3047 in modes 3, 4, and 6, addresses H'FF710 to H'FFF0F in the H8/3045
and H8/3044 in modes 1, 2, 5, and 7, and addresses H'FFF710 to H'FFFF0F in the H8/3045 and
H8/3044 in modes 3, 4, and 6 are directed to the on-chip RAM. In modes 1 to 6 (expanded
modes), when the RAME bit is cleared to 0, the off-chip address space is accessed. In mode 7
(single-chip mode), when the RAME bit is cleared to 0, the on-chip RAM is not accessed: read
access always results in H'FF data, and write access is ignored.
Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written
and read by word access. It can also be written and read by byte access. Byte data is accessed in
two states using the upper 8 bits of the data bus. Word data starting at an even address is accessed
in two states using all 16 bits of the data bus.
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