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(b) The V
bit in the flash memory control register (FLMCR) is set or cleared when the V
PP
bit in FLMCR is set or cleared while a voltage of 12.0 ± 0.6 V is being applied to the V
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After the V
E bit is set, it becomes possible to write the erase block registers (EBR1 and EBR2)
PP
and the EV, PV, E, and P bits in FLMCR. Accordingly, program or erase flash memory 5 to 10 µs
after the V
E bit is set. V
PP
are cleared. Be sure that these bits are not set by mistaken access to FLMCR.
ø
2.7 to 5.5 V
V
CC
0 to Vcc V
V
PP
12±0.6 V
0 to Vcc V
MD2
RES
V
E bit
PP
* t
Figure 18-28 Power-On and Power-Off Timing (Boot Mode)
should be turned off only when the P, E and V
PP
t
VPS
tosc1
12±0.6 V
min 0 µs
t
MDS
min 0µs
VppE
set
Period during which flash memory access is prohibited
Period during which flash memory can be rewritten
(Execution of program in flash memory prohibited, and data reads other than verify
operations prohibited)
: 5 to 10µs
VPS
Programming/
erasing
t
*
possible
FRS
min 10 ø
VppE
cleared
625
E
PP
pin.
PP
E bits in FLMCR
PP
min 0 µs
0 to Vcc V
0 to Vcc V
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