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ISR—IRQ Status Register
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Bit
7
—
Initial value
0
Read/Write
—
IRQ to IRQ flags
5
Bits 5 to 0
IRQ5F to IRQ0F
0
1
Note:
Only 0 can be written, to clear the flag.
*
6
5
4
—
IRQ5F
IRQ4F
0
0
0
—
R/(W) *
R/(W) *
0
Setting and Clearing Conditions
[Clearing conditions]
Read IRQnF when IRQnF = 1, then write 0 in IRQnF.
IRQn
IRQnSC = 0,
handling is carried out.
IRQnSC = 1 and IRQn interrupt exception handling is
carried out.
[Setting conditions]
IRQnSC = 0 and IRQn input is low.
IRQnSC = 1 and a falling edge is generated in the IRQn input.
822
H'F6
Interrupt controller
3
2
1
IRQ3F
IRQ2F
IRQ1F
0
0
0
R/(W) *
R/(W) *
R/(W) *
input is high, and interrupt exception
0
IRQ0F
0
R/(W) *
(n = 5 to 0)
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