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Figure 6-19 shows the timing when the bus right is requested by an external bus master during a
read cycle in a two-state-access area. There is a minimum interval of two states from when the
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BREQ signal goes low until the bus is released.
ø
Address
bus
CS
n
Data bus
AS
RD
,
High
HWR
LWR
,
BREQ
BACK
n = 7 to 0
BREQ
1
Low
signal is sampled at rise of T state.
BACK
2
signal goes low at end of CPU read cycle, releasing bus right to external bus master.
BREQ
3
pin continues to be sampled while bus is released to external bus master.
BREQ
4, 5
High
signal is sampled twice consecutively.
BREQ
6
signal goes high, ending bus-release cycle.
Figure 6-19 External-Bus-Released State (Two-State-Access Area, During Read Cycle)
CPU cycles
T
T
1
2
Address
Minimum 2 cycles
1
2
1
143
External bus released
High-impedance
High level
High-impedance
High-impedance
High-impedance
3
4
5
CPU cycles
6
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