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9.9.2 Register Descriptions
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Table 9-13 summarizes the registers of port 8.
Table 9-13 Port 8 Registers
Address*
Name
H'FFCD
Port 8 data direction
register
H'FFCF
Port 8 data register
Note: * Lower 16 bits of the address.
Port 8 Data Direction Register (P8DDR): P8DDR is an 8-bit write-only register that can select
input or output for each pin in port 8.
Bit
—
Initial value
Modes
1 to 4
Read/Write
—
Initial value
Modes
5 to 7
Read/Write
—
Modes 1 to 6 (Expanded Modes): When bits in P8DDR bit are set to 1, P8
to CS
output pins. When bits in P8DDR are cleared to 0, the corresponding pins become input
3
ports. In modes 1 to 4 (expanded modes with on-chip ROM disabled), following a reset only CS
is output. The other three pins are input ports. In modes 5 and 6 (expanded modes with on-chip
ROM enabled), following a reset all four pins are input ports.
When the refresh controller is enabled, P8
refresh controller is disabled, P8
setting. For details see table 9-15.
Mode 7 (Single-Chip Mode): Port 8 is a generic input/output port. A pin in port 8 becomes an
output port if the corresponding P8DDR bit is set to 1, and an input port if this bit is cleared to 0.
P8DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
Abbreviation
P8DDR
P8DR
7
6
5
—
—
1
1
1
—
—
1
1
1
—
—
Reserved bits
is used unconditionally for RFSH output. When the
0
becomes a generic input/output port according to the P8DDR
0
268
R/W
Mode 1 to 4
W
H'F0
R/W
H'E0
4
3
2
P8 DDR
P8 DDR
P8 DDR
4
3
2
1
0
0
W
W
W
0
0
0
W
W
W
Port 8 data direction 4 to 0
These bits select input or
output for port 8 pins
Initial Value
Mode 5 to 7
H'E0
H'E0
1
0
P8 DDR
P8 DDR
1
0
0
0
W
W
0
0
W
W
to P8
become CS
4
1
0
0
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