Hitachi H8/3048 Hardware Manual page 395

Contention between General Register Write and Compare Match: If a compare match occurs
in the T state of a general register write cycle, writing takes priority and the compare match
3
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signal is inhibited. See figure 10-64.
ø
Address bus
Internal write signal
TCNT
GR
Compare match signal
Figure 10-64 Contention between General Register Write and Compare Match
General register write cycle
T T T
1 2
GR address
N
N
General register write data
383
3
N + 1
M
Inhibited