Hitachi H8/3048 Hardware Manual page 756

Single-chip microcomputer
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DTCR0A—Data Transfer Control Register 0A
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Short address mode
Bit
7
DTE
Initial value
0
Read/Write
R/W
Data transfer select
Bit 2
DTS2
0
1
Data transfer interrupt enable
0 Interrupt requested by DTE bit is disabled
1 Interrupt requested by DTE bit is enabled
Repeat enable
RPE
DTIE
0
0
1
1
0
1
Data transfer increment/decrement
0 Incremented:
1 Decremented:
Data transfer size
0 Byte-size transfer
1 Word-size transfer
Data transfer enable
0 Data transfer is disabled
1 Data transfer is enabled
6
5
DTSZ
DTID
0
0
R/W
R/W
Bit 1
Bit 0
DTS1
DTS0
Data Transfer Activation Source
0
0
Compare match/input capture A interrupt from ITU channel 0
1
Compare match/input capture A interrupt from ITU channel 1
1
0
Compare match/input capture A interrupt from ITU channel 2
1
Compare match/input capture A interrupt from ITU channel 3
0
0
SCI0 transmit-data-empty interrupt
1
SCI0 receive-data-full interrupt
1
Transfer in full address mode (channel A)
0
Transfer in full address mode (channel A)
1
Description
I/O mode
Repeat mode
Idle mode
If DTSZ = 0, MAR is incremented by 1 after each transfer
If DTSZ = 1, MAR is incremented by 2 after each transfer
If DTSZ = 0, MAR is decremented by 1 after each transfer
If DTSZ = 1, MAR is decremented by 2 after each transfer
H'27
4
3
2
RPE
DTIE
DTS2
0
0
0
R/W
R/W
R/W
749
DMAC0
1
0
DTS0
DTS1
0
0
R/W
R/W

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