Hitachi H8/3048 Hardware Manual page 335

Bits 6 and 5—Counter Clear 1/0 (CCLR1, CCLR0): These bits select how TCNT is cleared.
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Bit 6 Bit 5
CCLR1 CCLR0
0 0
1
1 0
1
Notes: 1. TCNT is cleared by compare match when the general register functions as an output
compare register, and by input capture when the general register functions as an input
capture register.
2. Selected in TSNC.
Bits 4 and 3—Clock Edge 1/0 (CKEG1, CKEG0): These bits select external clock input edges
when an external clock source is used.
Bit 4 Bit 3
CKEG1 CKEG0 Description
0 0
1
1 —
When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in TCR2 are ignored.
Phase counting takes precedence.
Description
TCNT is not cleared
TCNT is cleared by GRA compare match or input capture
TCNT is cleared by GRB compare match or input capture
Synchronous clear: TCNT is cleared in synchronization with other
*2
synchronized timers
Count rising edges
Count falling edges
Count both edges
323
(Initial value)
*1
*1
(Initial value)