Table of Contents
Advertisement
www.DataSheet4U.com
D.1 Port States in Each Mode
Table D-1 Port States
Pin
Name
Mode
ø
—
RESO
—
P1
to P1
1 to 4
7
0
5, 6
7
P2
to P2
1 to 4
7
0
5, 6
7
P3
to P3
1 to 6
7
0
7
P4
to P4
1 to 6 8-bit bus
7
0
7
Legend
H:
High
L:
Low
T:
High-impedance state
keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register bit
Note: * Low output only when WDT overflow causes a reset.
Appendix D Pin States
Reset
Clock output T
T*
L
T
T
L
T
T
T
T
T
16-bit bus
T
T
Hardware Software
Bus-
Standby
Standby
Released
Mode
Mode
Mode
H
Clock output Clock output
T
T
T
T
T
T
T
keep
T
T
T
T
keep
—
T
T
T
T
keep
T
T
T
T
keep
—
T
T
T
T
keep
—
T
keep
keep
T
T
T
T
keep
—
849
Program
Execution,
Sleep Mode
RESO
A
to A
7
0
Input port
(DDR = 0)
A
to A
7
0
(DDR = 1)
I/O port
A
to A
15
8
Input port
(DDR = 0)
A
to A
15
8
(DDR = 1)
I/O port
D
to D
15
8
I/O port
I/O port
D
to D
7
0
I/O port
Advertisement
Table of Contents
