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H8/3048 Series
CS
0
CS
1
CS
2
WAIT
RD
HWR
LWR
A
to A
23
0
D
to D
15
8
D to D
7
0
Figure 6-18 Interconnections with Memory (Example)
A
to A
18
1
SRAM1 (even addresses)
A
to A
15
1
SRAM2 (odd addresses)
A
to A
15
1
A
to A
14
0
140
EPROM
A
to A
17
0
I/O
to I/O
15
8
I/O to I/O
7
0
CE
OE
A
to A
14
0
I/O to I/O
7
0
CS
OE
WE
A
to A
14
0
I/O to I/O
7
0
CS
OE
WE
SRAM3
A
to A
14
0
I/O to I/O
7
0
CS
OE
WE
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