Hitachi H8/3048 Hardware Manual page 387

Timing of Disabling of ITU Output by External Trigger: If the XTGD bit is cleared to 0 in
TOCR in reset-synchronized PWM mode or complementary PWM mode, when an input capture
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A signal occurs in channel 1, the master enable bits are cleared to 0 in TOER, disabling ITU
output. Figure 10-55 shows the timing.
ø
TIOCA pin
1
Input capture
signal
TOER
ITU output
pins
N: Arbitrary setting (H'C1 to H'FF)
Figure 10-55 Timing of Disabling of ITU Output by External Trigger (Example)
Timing of Output Inversion by TOCR: The output levels in reset-synchronized PWM mode and
complementary PWM mode can be inverted by inverting the output level select bits (OLS4 and
OLS3) in TOCR. Figure 10-56 shows the timing.
ø
Address bus
TOCR
ITU output pin
Figure 10-56 Timing of Inverting of ITU Output Level by Writing to TOCR (Example)
N
ITU output
ITU output
T T T
1 2 3
TOCR address
H'C0 N
I/O port ITU output
Generic
ITU output
input/output
Inverted
375
H'C0
I/O port
Generic
input/output