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(1) Data write
(2) Transfer from
TDR to TSR
(3) Serial data output
In case of normal transmission: TEND flag is set
In case of transmit error:
Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first
transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has
been completed.
Figure 14-5 Relation Between Transmit Operation and Internal Registers
DS
Da
I/O data
TXI
(TEND interrupt)
Figure 14-6 TEND Flag Occurrence Timing
TDR
TSR
(shift register)
Data 1
Data 1
Data 1
Data 1
ERS flag is set
Steps (2) and (3) above are repeated until the TEND flag is set
Db
Dc
Dd
De
Df
12.5 etu
11.0 etu
514
; Data remains in TDR
Data 1
I/O signal line output
Dg
Dh
Dp
DE
Guard
GM = 0
GM = 1
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