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Bit 5—Address 21 Enable (A21E): Enables PA
Writing 0 in this bit enables A
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cannot be modified and PA
Bit 5
A21E
Description
0
PA
is the A
6
1
PA
is the PA
6
Bits 4 to 1—Reserved: Read-only bits, always read as 1.
Bit 0—Bus Release Enable (BRLE): Enables or disables release of the bus to an external device.
Bit 0
BRLE
Description
The bus cannot be released to an external device; BREQ and BACK
0
can be used as input/output pins
1
The bus can be released to an external device
6.2.6 Chip Select Control Register (CSCR)
CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals
(CS
to CS
).
7
4
If a chip select signal (CS
functions as a chip select signal (CS
functions. CSCR cannot be modified in single-chip mode.
Bit
Initial value
Read/Write
CSCR is initialized to H'0F by a reset and in hardware standby mode. It is not initialized in
software standby mode.
address output from PA
21
has its ordinary input/output functions.
6
address output pin
21
/TP
/TIOCA
input/output pin
6
6
2
to CS
) output is selected in this register, the corresponding pin
7
4
to CS
) output, this function taking priority over other
7
4
7
6
5
CS7E
CS6E
CS5E
0
0
0
R/W
R/W
R/W
Chip select 7 to 4 enable
These bits enable or disable
chip select signal output
to be used as the A
6
21
. In modes other than 3, 4, and 6 this bit
6
4
3
CS4E
—
0
1
R/W
—
Reserved bits
119
address output pin.
(Initial value)
(Initial value)
2
0
1
—
—
—
1
1
1
—
—
—
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