Hitachi H8/3048 Hardware Manual page 228

Single-chip microcomputer
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The transfer count is specified as an 8-bit value in ETCRH and ETCRL. The maximum transfer
count is 255, obtained by setting both ETCRH and ETCRL to H'FF.
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Transfers can be requested (activated) by compare match/input capture A interrupts from ITU
channels 0 to 3, transmit-data-empty and receive-data-full interrupts from SCI channel 0, and
external request signals.
For the detailed settings see section 8.2.4, Data Transfer Control Registers (DTCR).
Figure 8-7 shows a sample setup procedure for repeat mode.
Repeat mode
Set source and
destination addresses
Set transfer count
Read DTCR
Set DTCR
Repeat mode
Figure 8-7 Repeat Mode Setup Procedure (Example)
1.
Set the source and destination addresses in MAR
and IOAR. The transfer direction is determined
automatically from the activation source.
2.
Set the transfer count in both ETCRH and ETCRL.
1
3.
Read DTCR while the DTE bit is cleared to 0.
4.
Set the DTCR bits as follows.
Select the DMAC activation source with bits
DTS2 to DTS0.
Clear the DTIE bit to 0 and set the RPE bit to 1
2
to select repeat mode.
Select MAR increment or decrement with the DTID bit.
Select byte size or word size with the DTSZ bit.
Set the DTE bit to 1 to enable the transfer.
3
4
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