Table of Contents
Advertisement
www.DataSheet4U.com
ø
Address bus
CS
n
AS
RD
Read
D
to D
15
access
D to D
7
HWR
LWR
Write
access
D
to D
15
D to D
7
Note: n = 7 to 0
Figure 6-11 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3)
T
1
External address in area n
8
0
8
0
(Word Access)
132
Bus cycle
T
2
Valid
Valid
Valid
Valid
Advertisement
Table of Contents
