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RFSHCR—Refresh Control Register
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Bit
SRFMD
Initial value
Read/Write
R/W
Self-refresh mode
0 DRAM or PSRAM self-refresh is disabled in software standby mode
1 DRAM or PSRAM self-refresh is enabled in software standby mode
7
6
5
PSRAME
DRAME
0
0
0
R/W
R/W
Refresh pin enable
0
1
Address multiplex mode select
0 8-bit column mode
1 9-bit column mode
Strobe mode select
WE
0 2
mode
CAS
1 2
mode
PSRAM enable, DRAM enable
Bit 6
Bit 5
PSRAME DRAME
RAM Interface
0
0
Can be used as an interval timer
(DRAM and PSRAM cannot be
directly connected)
1
DRAM can be directly connected
1
0
PSRAM can be directly connected
1
Illegal setting
H'AC
4
3
WE
M8
CAS/
M9/
RFSHE
0
0
R/W
R/W
R/W
Refresh cycle enable
0 Refresh cycles are disabled
1 Refresh cycles are enabled for area 3
Refresh signal output at the
Refresh signal output at the
793
Refresh controller
2
1
0
—
RCYCE
0
1
0
—
R/W
RFSH
pin is disabled
RFSH
pin is enabled
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