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Figure 8-16 shows the timing when the DMAC is activated by the falling edge of DREQ in normal
mode.
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T
T
2
ø
DREQ
Address
bus
RD
HWR
LWR
,
Figure 8-16 Timing of DMAC Activation by Falling Edge of DREQ in Normal Mode
CPU cycle
T
T
T
T
T
1
2
1
2
d
Minimum 4 states
228
CPU
DMAC cycle
cycle
T
T
T
T
T
1
2
1
2
1
Next sampling point
DMAC cycle
T
T
T
2
d
1
2
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