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External Clock: The external clock frequency should be equal to the system clock frequency
(ø) when not divided by the on-chip frequency divider. Table 19-3, figures 19-6 and 19-7
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indicate the clock timing.
When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by
the on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to
external devices after the external clock settling time (t
The system must remain reset with the reset signal low during t
unstable.
Table 19-3 Clock Timing
Item
External clock input
low pulse width
External clock input
high pulse width
External clock rise
time
External clock fall
time
Clock low pulse
width
Clock high pulse
width
External clock
output settling
delay time
Note: * t
includes 10 t
DEXT
V
=
CC
2.7 V to 5.5 V
Symbol
Min
Max
t
40
—
EXL
t
40
—
EXH
t
—
10
EXr
t
—
10
EXf
t
0.4
0.6
CL
80
—
t
0.4
0.6
CH
80
—
t
500
—
*
DEXT
RES (t
of
).
cyc
RESW
) has passed after the clock input.
DEXT
, while the clock output is
DEXT
V
= 5.0 V ± 10%
CC
Min
Max
20
—
20
—
—
5
—
5
0.4
0.6
80
—
0.4
0.6
80
—
500
—
637
Unit Test Conditions
ns
Figure 19-6
ns
ns
ns
ø ≥ 5 MHz
t
Figure
cyc
21-7
ns
ø < 5 MHz
ø ≥ 5 MHz
t
cyc
ns
ø < 5 MHz
µs
Figure 19-7
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