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8.3.4 Data Transfer Control Registers (DTCR)
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The data transfer control registers (DTCRs) are 8-bit readable/writable registers that control the
operation of the DMAC channels. A channel operates in full address mode when bits DTS2A and
DTS1A are both set to 1 in DTCRA. DTCRA and DTCRB have different functions in full address
mode.
DTCRA
Bit
Initial value
Read/Write
Data transfer enable
Enables or disables
data transfer
DTCRA is initialized to H'00 by a reset and in standby mode.
7
6
5
DTE
DTSZ
SAID
0
0
0
R/W
R/W
R/W
Data transfer size
Selects byte or
word size
Source address
increment/decrement
Source address increment/
decrement enable
These bits select whether
the source address register
(MARA) is incremented,
decremented, or held fixed
during the data transfer
4
3
2
SAIDE
DTIE
DTS2A
0
0
0
R/W
R/W
R/W
Data transfer
interrupt enable
Enables or disables the
CPU interrupt at the end
of the transfer
Data transfer select
2A and 1A
These bits must both be
set to 1
199
1
0
DTS1A
DTS0A
0
0
R/W
R/W
Data transfer
select 0A
Selects block
transfer mode
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