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Reset
Exception
Interrupt
sources
Trap instruction
Figure 2-12 Classification of Exception Sources
End of bus
release
Bus-released state
End of
exception
handling
Exception-handling state
RES = 1
*1
Reset state
Notes: 1.
From any state except hardware standby mode, a transition to the reset state occurs
RES
whenever
2.
From any state, a transition to hardware standby mode occurs when
External interrupts
Internal interrupts (from on-chip supporting modules)
End of bus release
Bus request
Program execution state
Bus
request
Exception
Interrupt
NMI, IRQ , IRQ ,
0
1
or IRQ interrupt
2
STBY
RES
= 1,
= 0
goes low.
Figure 2-13 State Transitions
48
SLEEP
instruction
with SSBY = 0
Sleep mode
SLEEP instruction
with SSBY = 1
Software standby mode
Hardware standby mode
Power-down state
STBY
goes low.
*2
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