Hitachi HD64F3048 Manuals

Manuals and User Guides for Hitachi HD64F3048. We have 3 Hitachi HD64F3048 manuals available for free PDF download: Hardware Manual

Hitachi HD64F3048 Hardware Manual

Hitachi HD64F3048 Hardware Manual (867 pages)

Single-Chip Microcomputer

Brand: Hitachi | Category: Computer Hardware | Size: 3 MB

Table of Contents

Table of Contents
3
Overview
16
Block Diagram
20
Pin Description
21
Pin Arrangement
21
Pin Assignments in each Mode
22
Pin Functions
25
Cpu
30
Overview
30
Features
30
Differences from H8/300 CPU
31
CPU Operating Modes
32
Address Space
33
Register Configuration
34
Overview
34
General Registers
35
Control Registers
36
Initial CPU Register Values
37
Data Formats
38
General Register Data Formats
38
Memory Data Formats
40
Instruction Set
41
Instruction Set Overview
41
Instructions and Addressing Modes
42
Tables of Instructions Classified by Function
43
Basic Instruction Formats
53
Notes on Use of Bit Manipulation Instructions
54
Addressing Modes and Effective Address Calculation
54
Addressing Modes
54
Effective Address Calculation
57
Processing States
61
Overview
61
Program Execution State
62
Exception-Handling State
62
Exception-Handling Sequences
64
Bus-Released State
65
Reset State
65
Power-Down State
65
Basic Operational Timing
66
Overview
66
On-Chip Memory Access Timing
66
On-Chip Supporting Module Access Timing
68
Access to External Address Space
69
MCU Operating Modes
70
Overview
70
Operating Mode Selection
70
Register Configuration
71
Mode Control Register (MDCR)
72
System Control Register (SYSCR)
73
Operating Mode Descriptions
75
Mode 1
75
Mode 2
75
Mode 3
75
Mode 4
75
Mode 5
75
Mode 6
75
Mode 7
76
Pin Functions in each Operating Mode
76
Memory Map in each Operating Mode
76
Exception Handling
85
Overview
85
Exception Handling Types and Priority
85
Exception Handling Operation
85
Exception Vector Table
86
Reset
87
Overview
87
Reset Sequence
87
Interrupts after Reset
90
Interrupts
91
Trap Instruction
92
Stack Status after Exception Handling
93
Notes on Stack Usage
94
Interrupt Controller
95
Overview
95
Features
95
Block Diagram
96
Pin Configuration
97
Register Descriptions
98
System Control Register (SYSCR)
98
Interrupt Priority Registers a and B (IPRA, IPRB)
99
IRQ Status Register (ISR)
106
IRQ Enable Register (IER)
107
IRQ Sense Control Register (ISCR)
108
Interrupt Sources
109
External Interrupts
109
Internal Interrupts
110
Interrupt Vector Table
110
Interrupt Operation
114
Interrupt Handling Process
114
Interrupt Sequence
119
Interrupt Response Time
120
Usage Notes
121
Contention between Interrupt and Interrupt-Disabling Instruction
121
Instructions that Inhibit Interrupts
122
Interrupts During EEPMOV Instruction Execution
122
Notes on External Interrup to During Use
122
Bus Controller
125
Overview
125
Features
125
Block Diagram
126
Input/Output Pins
127
Register Configuration
127
Bus Width Control Register ABWCR
127
Register Descriptions
128
Access State Control Register (ASTCR)
129
Wait Control Register (WCR)
130
Wait State Controller Enable Register (WCER)
131
Bus Release Control Register (BRCR)
132
Chip Select Control Register (CSCR)
133
Operation
135
Area Division
135
Chip Select Signals
136
Data Bus
138
Bus Control Signal Timing
139
Wait Modes
147
Interconnections with Memory (Example)
153
Bus Arbiter Operation
155
Usage Notes
158
Connection to Dynamic RAM and Pseudo-Static RAM
158
Register Write Timing
158
BREQ Input Timing
160
Transition to Software Standby Mode
160
Refresh Controller
161
Overview
161
Features
161
Block Diagram
162
Input/Output Pins
163
Register Configuration
163
Register Descriptions
164
Refresh Control Register (RFSHCR)
164
Refresh Timer Control/Status Register (RTMCSR)
167
Refresh Timer Counter (RTCNT)
169
Refresh Time Constant Register (RTCOR)
169
Operation
170
Overview
170
DRAM Refresh Control
171
Pseudo-Static RAM Refresh Control
186
Interval Timing
191
Interrupt Source
197
Usage Notes
197
DMA Controller
199
Overview
199
Features
199
Block Diagram
200
Functional Overview
201
Input/Output Pins
202
Register Configuration
202
Register Descriptions (Short Address Mode)
204
Memory Address Registers (MAR)
204
I/O Address Registers (IOAR)
205
Execute Transfer Count Registers (ETCR)
205
Data Transfer Control Registers (DTCR)
207
Register Descriptions (Full Address Mode)
210
Memory Address Registers (MAR)
210
I/O Address Registers (IOAR)
210
Execute Transfer Count Registers (ETCR)
211
Www.datasheet4U.com
211
Data Transfer Control Registers (DTCR)
213
Operation
219
Overview
219
I/O Mode
221
Idle Mode
223
Repeat Mode
226
Normal Mode
229
Block Transfer Mode
232
DMAC Activation
237
DMAC Bus Cycle
239
Multiple-Channel Operation
245
External Bus Requests, Refresh Controller, and DMAC
246
NMI Interrupts and DMAC
247
Aborting a DMA Transfer
248
Exiting Full Address Mode
249
DMAC States in Reset State, Standby Modes, and Sleep Mode
250
Interrupts
251
Usage Notes
252
Note on Word Data Transfer
252
DMAC Self-Access
252
Longword Access to Memory Address Registers
252
Note on Full Address Mode Setup
252
Note on Activating DMAC by Internal Interrupts
253
NMI Interrupts and Block Transfer Mode
254
Memory and I/O Address Register Values
254
Bus Cycle When Transfer Is Aborted
255
I/O Ports
256
Overview
259
Overview
262
Overview
266
Overview
268
Overview
272
Overview
278
Port 7
279
Register Description
279
Overview
280
Register Descriptions
281
Port 9
285
Overview
285
Register Descriptions
285
Port a
289
Overview
289
Register Descriptions
291
Pin Functions
292
Port B
297
Overview
297
Register Descriptions
299
Pin Functions
302
16-Bit Integrated Timer Unit (ITU)
307
Overview
307
Section 20.6, Module Standby Function
307
Features
307
Block Diagrams
310
Input/Output Pins
315
Register Configuration
316
Register Descriptions
319
Timer Start Register (TSTR)
319
Timer Synchro Register (TSNC)
320
Timer Mode Register (TMDR)
322
Timer Function Control Register (TFCR)
325
Timer Output Master Enable Register (TOER)
327
Timer Output Control Register (TOCR)
330
Timer Counters (TCNT)
331
General Registers (GRA, GRB)
332
Buffer Registers (BRA, BRB)
333
Timer Control Registers (TCR)
334
Timer I/O Control Register (TIOR)
336
Timer Status Register (TSR)
338
Timer Interrupt Enable Register (TIER)
341
CPU Interface
343
16-Bit Accessible Registers
343
8-Bit Accessible Registers
345
Operation
347
Overview
347
Basic Functions
348
Synchronization
358
PWM Mode
360
Reset-Synchronized PWM Mode
364
Complementary PWM Mode
367
Phase Counting Mode
377
Buffering
379
ITU Output Timing
386
Interrupts
388
Setting of Status Flags
388
Clearing of Status Flags
390
Interrupt Sources and DMA Controller Activation
391
Usage Notes
392
Programmable Timing Pattern Controller
407
Overview
407
Features
407
Block Diagram
408
TPC Pins
409
Registers
410
Register Descriptions
411
Port a Data Direction Register (PADDR)
411
Port a Data Register (PADR)
411
Port B Data Direction Register (PBDDR)
412
Port B Data Register (PBDR)
412
Next Data Register a (NDRA)
413
Next Data Register B (NDRB)
415
Next Data Enable Register a (NDERA)
417
Next Data Enable Register B (NDERB)
418
TPC Output Control Register (TPCR)
419
TPC Output Mode Register (TPMR)
422
Section 11.3.4, Non-Overlapping TPC Output
422
Operation
424
Overview
424
Output Timing
425
Normal TPC Output
426
Non-Overlapping TPC Output
428
TPC Output Triggering by Input Capture
430
Usage Notes
431
Operation of TPC Output Pins
431
Note on Non-Overlapping Output
431
Watchdog Timer
433
Overview
433
Features
433
Block Diagram
434
Pin Configuration
434
Register Configuration
435
Register Descriptions
436
Timer Counter (TCNT)
436
Timer Control/Status Register (TCSR)
437
Section 12.2.4, Notes on Register Access
437
Reset Control/Status Register (RSTCSR)
439
Notes on Register Access
441
Operation
443
Watchdog Timer Operation
443
Interval Timer Operation
444
Timing of Setting of Overflow Flag (OVF)
445
Timing of Setting of Watchdog Timer Reset Bit (WRST)
446
Interrupts
447
Usage Notes
447
Serial Communication Interface
448
Overview
448
Features
448
Block Diagram
450
Input/Output Pins
451
Register Configuration
451
Register Descriptions
452
Receive Shift Register (RSR)
452
Receive Data Register (RDR)
452
Transmit Shift Register (TSR)
453
Transmit Data Register (TDR)
453
Serial Mode Register (SMR)
454
Section 13.2.8, Bit Rate Register (BRR)
457
Serial Control Register (SCR)
458
Serial Status Register (SSR)
462
Bit Rate Register (BRR)
466
Operation
475
Overview
475
Operation in Asynchronous Mode
477
Multiprocessor Communication
486
Synchronous Operation
493
Transmitting and Receiving Data
494

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Hitachi HD64F3048 Hardware Manual

Hitachi HD64F3048 Hardware Manual (867 pages)

Single-Chip Microcomputer

Brand: Hitachi | Category: Computer Hardware | Size: 2 MB

Table of Contents

Table of Contents
3
Overview
16
Block Diagram
20
Pin Description
21
Pin Arrangement
21
Pin Assignments in each Mode
22
Pin Functions
25
Cpu
30
Overview
30
Features
30
Differences from H8/300 CPU
31
CPU Operating Modes
32
Address Space
33
Register Configuration
34
Overview
34
General Registers
35
Control Registers
36
Initial CPU Register Values
37
Data Formats
38
General Register Data Formats
38
Memory Data Formats
40
Instruction Set
41
Instruction Set Overview
41
Instructions and Addressing Modes
42
Tables of Instructions Classified by Function
43
Basic Instruction Formats
53
Notes on Use of Bit Manipulation Instructions
54
Addressing Modes and Effective Address Calculation
54
Addressing Modes
54
Effective Address Calculation
57
Processing States
61
Overview
61
Program Execution State
62
Exception-Handling State
62
Exception-Handling Sequences
64
Bus-Released State
65
Reset State
65
Power-Down State
65
Basic Operational Timing
66
Overview
66
On-Chip Memory Access Timing
66
On-Chip Supporting Module Access Timing
68
Access to External Address Space
69
Section 3 MCU Operating Modes
70
Overview
70
Operating Mode Selection
70
Register Configuration
71
Mode Control Register (MDCR)
72
System Control Register (SYSCR)
73
Operating Mode Descriptions
75
Mode 1
75
Mode 2
75
Mode 3
75
Mode 4
75
Mode 5
75
Mode 6
75
Mode 7
76
Pin Functions in each Operating Mode
76
Memory Map in each Operating Mode
76
Exception Handling
85
Overview
85
Exception Handling Types and Priority
85
Exception Handling Operation
85
Exception Vector Table
86
Reset
87
Overview
87
Reset Sequence
87
Interrupts after Reset
90
Interrupts
91
Trap Instruction
92
Stack Status after Exception Handling
93
Notes on Stack Usage
94
Interrupt Controller
95
Overview
95
Features
95
Block Diagram
96
Pin Configuration
97
Register Configuration
97
Register Descriptions
98
System Control Register (SYSCR)
98
Interrupt Priority Registers a and B (IPRA, IPRB)
99
IRQ Status Register (ISR)
106
IRQ Enable Register (IER)
107
IRQ Sense Control Register (ISCR)
108
Interrupt Sources
109
External Interrupts
109
Internal Interrupts
110
Interrupt Vector Table
110
Interrupt Operation
114
Interrupt Handling Process
114
Interrupt Sequence
119
Interrupt Response Time
120
Usage Notes
121
Contention between Interrupt and Interrupt-Disabling Instruction
121
Instructions that Inhibit Interrupts
122
Interrupts During EEPMOV Instruction Execution
122
Notes on External Interrup to During Use
122
Bus Controller
125
Overview
125
Features
125
Block Diagram
126
Input/Output Pins
127
Register Configuration
127
Register Descriptions
128
Bus Width Control Register (ABWCR)
128
Access State Control Register (ASTCR)
129
Wait Control Register (WCR)
130
Wait State Controller Enable Register (WCER)
131
Bus Release Control Register (BRCR)
132
Chip Select Control Register (CSCR)
133
Operation
135
Area Division
135
Chip Select Signals
136
Data Bus
138
Bus Control Signal Timing
139
Wait Modes
147
Interconnections with Memory (Example)
153
Bus Arbiter Operation
155
Usage Notes
158
Connection to Dynamic RAM and Pseudo-Static RAM
158
Register Write Timing
158
BREQ Input Timing
160
Transition to Software Standby Mode
160
Refresh Controller
161
Overview
161
Features
161
Block Diagram
162
Input/Output Pins
163
Register Configuration
163
Register Descriptions
164
Refresh Control Register (RFSHCR)
164
Refresh Timer Control/Status Register (RTMCSR)
167
Refresh Timer Counter (RTCNT)
169
Refresh Time Constant Register (RTCOR)
169
Operation
170
Overview
170
DRAM Refresh Control
171
Pseudo-Static RAM Refresh Control
186
Interval Timing
191
Interrupt Source
197
Usage Notes
197
DMA Controller
199
Overview
199
Features
199
Block Diagram
200
Functional Overview
201
Input/Output Pins
202
Register Configuration
202
Register Descriptions (Short Address Mode)
204
Memory Address Registers (MAR)
204
I/O Address Registers (IOAR)
205
Execute Transfer Count Registers (ETCR)
205
Data Transfer Control Registers (DTCR)
207
Register Descriptions (Full Address Mode)
210
Memory Address Registers (MAR)
210
I/O Address Registers (IOAR)
210
Execute Transfer Count Registers (ETCR)
211
Data Transfer Control Registers (DTCR)
213
Operation
219
Overview
219
I/O Mode
221
Idle Mode
223
Repeat Mode
226
Normal Mode
229
Block Transfer Mode
232
DMAC Activation
237
DMAC Bus Cycle
239
Multiple-Channel Operation
245
External Bus Requests, Refresh Controller, and DMAC
246
NMI Interrupts and DMAC
247
Aborting a DMA Transfer
248
Exiting Full Address Mode
249
DMAC States in Reset State, Standby Modes, and Sleep Mode
250
Interrupts
251
Usage Notes
252
Note on Word Data Transfer
252
DMAC Self-Access
252
Longword Access to Memory Address Registers
252
Note on Full Address Mode Setup
252
Note on Activating DMAC by Internal Interrupts
253
NMI Interrupts and Block Transfer Mode
254
Memory and I/O Address Register Values
254
Bus Cycle When Transfer Is Aborted
255
I/O Ports
256
Overview
256
Register Descriptions
269
Overview
275
Port 7
279
Port a
289
Overview
289
Register Descriptions
291
Pin Functions
294
Port B
297
Overview
297
Register Descriptions
299
Pin Functions
301
16-Bit Integrated Timer Unit (ITU)
307
Overview
307
Section 20.6, Module Standby Function
307
Features
307
Block Diagrams
310
Input/Output Pins
315
Register Configuration
316
Register Descriptions
319
Timer Start Register (TSTR)
319
Timer Synchro Register (TSNC)
320
Timer Mode Register (TMDR)
322
Timer Function Control Register (TFCR)
325
Timer Output Master Enable Register (TOER)
327
Timer Output Control Register (TOCR)
330
Timer Counters (TCNT)
331
General Registers (GRA, GRB)
332
Buffer Registers (BRA, BRB)
333
Timer Control Registers (TCR)
334
Timer I/O Control Register (TIOR)
336
Timer Status Register (TSR)
338
Timer Interrupt Enable Register (TIER)
341
CPU Interface
343
16-Bit Accessible Registers
343
8-Bit Accessible Registers
345
Operation
347
Overview
347
Basic Functions
348
Complementary PWM Mode
348
Phase Counting Mode
377
Buffering
379
ITU Output Timing
386
Interrupts
388
Setting of Status Flags
388
Clearing of Status Flags
390
Interrupt Sources and DMA Controller Activation
391
Usage Notes
392
Programmable Timing Pattern Controller
407
Overview
407
Features
407
Block Diagram
408
TPC Pins
409
Registers
410
Register Descriptions
411
Port a Data Direction Register (PADDR)
411
Port a Data Register (PADR)
411
Port B Data Direction Register (PBDDR)
412
Port B Data Register (PBDR)
412
Next Data Register a (NDRA)
413
Next Data Register B (NDRB)
415
Next Data Enable Register a (NDERA)
417
Next Data Enable Register B (NDERB)
418
TPC Output Control Register (TPCR)
419
TPC Output Mode Register (TPMR)
422
Section 11.3.4, Non-Overlapping TPC Output
422
Operation
424
Overview
424
Output Timing
425
Normal TPC Output
426
Non-Overlapping TPC Output
428
TPC Output Triggering by Input Capture
430
Usage Notes
431
Operation of TPC Output Pins
431
Note on Non-Overlapping Output
431
Watchdog Timer
433
Overview
433
Features
433
Block Diagram
434
Pin Configuration
434
Register Configuration
435
Register Descriptions
436
Timer Counter (TCNT)
436
Timer Control/Status Register (TCSR)
437
Section 12.2.4, Notes on Register Access
437
Reset Control/Status Register (RSTCSR)
439
Notes on Register Access
441
Operation
443
Watchdog Timer Operation
443
Interval Timer Operation
444
Timing of Setting of Overflow Flag (OVF)
445
Timing of Setting of Watchdog Timer Reset Bit (WRST)
446
Interrupts
447
Usage Notes
447
Serial Communication Interface
448
Overview
448
Features
448
Block Diagram
450
Input/Output Pins
451
Register Configuration
451
Register Descriptions
452
Transmit Shift Register (TSR)
453
Transmit Data Register (TDR)
453
Serial Mode Register (SMR)
454
Section 13.2.8, Bit Rate Register (BRR)
457
Serial Control Register (SCR)
458
Serial Status Register (SSR)
462
Bit Rate Register (BRR)
466
Operation
475
Overview
475
Operation in Asynchronous Mode
477
Multiprocessor Communication
486
Synchronous Operation
493
SCI Interrupts
502
Usage Notes
503
Smart Card Interface
507

Hitachi HD64F3048 Hardware Manual

Hitachi HD64F3048 Hardware Manual (867 pages)

Single-Chip Microcomputer

Brand: Hitachi | Category: Computer Hardware | Size: 2 MB

Table of Contents

Table of Contents
3
Overview

16
- Block Diagram
  20
- Pin Description
  21
  - Pin Arrangement
    21
  - Pin Assignments in each Mode
    22
  - Pin Functions
    25
Cpu

30
- Overview
  30
  - Features
    30
  - Differences from H8/300 CPU
    31
- CPU Operating Modes
  32
- Address Space
  33
- Register Configuration
  34
  - Overview
    34
  - General Registers
    35
  - Control Registers
    36
  - Initial CPU Register Values
    37
- Data Formats
  38
  - General Register Data Formats
    38
  - Memory Data Formats
    40
- Instruction Set
  41
- Addressing Modes and Effective Address Calculation
  54
  - Addressing Modes
    54
  - Effective Address Calculation
    57
- Processing States
  61
  - Overview
    61
  - Program Execution State
    62
  - Exception-Handling State
    62
  - Exception-Handling Sequences
    64
  - Bus-Released State
    65
  - Reset State
    65
  - Power-Down State
    65
- Basic Operational Timing
  66
MCU Operating Modes

70
- Overview
  70
  - Operating Mode Selection
    70
  - Register Configuration
    71
- Mode Control Register (MDCR)
  72
- System Control Register (SYSCR)
  73
- Operating Mode Descriptions
  75
  - Mode 1
    75
  - Mode 2
    75
  - Mode 3
    75
  - Mode 4
    75
  - Mode 5
    75
  - Mode 6
    75
  - Mode 7
    76
- Pin Functions in each Operating Mode
  76
- Memory Map in each Operating Mode
  76
Exception Handling

85
- Overview
  85
- Reset
  87
  - Overview
    87
  - Reset Sequence
    87
  - Interrupts after Reset
    90
- Interrupts
  91
- Trap Instruction
  92
- Stack Status after Exception Handling
  93
- Notes on Stack Usage
  94
Interrupt Controller

95
- Overview
  95
  - Features
    95
  - Block Diagram
    96
  - Pin Configuration
    97
  - Register Configuration
    97
  - System Control Register (SYSCR)
    97
  - Interrupt Priority Registers a and B (IPRA, IPRB)
    99
  - IRQ Status Register (ISR)
    106
  - IRQ Enable Register (IER)
    107
  - IRQ Sense Control Register (ISCR)
    108
- Interrupt Sources
  109
  - External Interrupts
    109
  - Internal Interrupts
    110
  - Interrupt Vector Table
    110
- Interrupt Operation
  114
  - Interrupt Handling Process
    114
  - Interrupt Sequence
    119
  - Interrupt Response Time
    120
- Usage Notes
  121
Bus Controller

125
- Overview
  125
  - Features
    125
  - Block Diagram
    126
  - Input/Output Pins
    127
  - Register Configuration
    127
- Register Descriptions
  128
- Operation
  135
  - Area Division
    135
  - Chip Select Signals
    136
  - Data Bus
    138
  - Bus Control Signal Timing
    139
  - Wait Modes
    147
  - Interconnections with Memory (Example)
    153
  - Bus Arbiter Operation
    155
  - Connection to Dynamic RAM and Pseudo-Static RAM
    158
  - Register Write Timing
    158
  - BREQ Input Timing
    160
  - Transition to Software Standby Mode
    160
Refresh Controller

161
- Overview
  161
  - Features
    161
  - Block Diagram
    162
  - Input/Output Pins
    163
  - Register Configuration
    163
- Register Descriptions
  164
- Operation
  170
  - DRAM Refresh Control
    171
  - Pseudo-Static RAM Refresh Control
    186
  - Interval Timing
    191
- Interrupt Source
  197
- Usage Notes
  197
DMA Controller

199
- Overview
  199
  - Features
    199
  - Block Diagram
    200
  - Functional Overview
    201
  - Input/Output Pins
    202
  - Register Configuration
    202
- Register Descriptions (Short Address Mode)
  204
- Register Descriptions (Full Address Mode)
  210
  - Memory Address Registers (MAR)
    210
  - I/O Address Registers (IOAR)
    210
- Www.datasheet4U.com
  211
  - Execute Transfer Count Registers (ETCR)
    211
  - Data Transfer Control Registers (DTCR)
    213
- Operation
  219
  - Overview
    219
  - I/O Mode
    221
  - Idle Mode
    223
  - Repeat Mode
    226
  - Normal Mode
    229
  - Block Transfer Mode
    232
  - DMAC Activation
    237
  - DMAC Bus Cycle
    239
  - Multiple-Channel Operation
    245
  - External Bus Requests, Refresh Controller, and DMAC
    246
  - NMI Interrupts and DMAC
    247
  - Aborting a DMA Transfer
    248
  - Exiting Full Address Mode
    249
  - DMAC States in Reset State, Standby Modes, and Sleep Mode
    250
- Interrupts
  251
- Usage Notes
  252
I/O Ports

256
- Overview
  256
- Port 1
  259
  - Overview
    259
  - Register Descriptions
    269
- Port 2
  272
  - Overview
    272
  - Register Descriptions
    275
- Port 3
  275
- Port 4
  275
  - Overview
    278
- Port 7
  279
  - Overview
    280
- Port 8
  285
- Port 9
  285
- Port a
  289
  - Register Descriptions
    291
  - Pin Functions
    292
- Port B
  297
  - Register Descriptions
    299
  - Pin Functions
    301
16-Bit Integrated Timer Unit (ITU)

307
- Overview
  307
  - Features
    307
  - Block Diagrams
    310
  - Input/Output Pins
    315
  - Register Configuration
    316
- Register Descriptions
  319
  - Timer Start Register (TSTR)
    319
  - Timer Synchro Register (TSNC)
    320
  - Timer Mode Register (TMDR)
    322
  - Timer Function Control Register (TFCR)
    325
  - Timer Output Master Enable Register (TOER)
    327
  - Timer Output Control Register (TOCR)
    330
  - Timer Counters (TCNT)
    331
  - General Registers (GRA, GRB)
    332
  - Buffer Registers (BRA, BRB)
    333
  - Timer Control Registers (TCR)
    334
  - Timer I/O Control Register (TIOR)
    336
  - Timer Status Register (TSR)
    338
  - Timer Interrupt Enable Register (TIER)
    341
- CPU Interface
  343
  - 16-Bit Accessible Registers
    343
  - 8-Bit Accessible Registers
    345
- Operation
  347
  - Overview
    347
  - Basic Functions
    348
  - Complementary PWM Mode
    348
  - Phase Counting Mode
    377
  - Buffering
    379
  - ITU Output Timing
    386
- Interrupts
  388
- Usage Notes
  392
Programmable Timing Pattern Controller

407
- Overview
  407
  - Features
    407
  - Block Diagram
    408
  - TPC Pins
    409
  - Registers
    410
- Register Descriptions
  411
  - Port a Data Direction Register (PADDR)
    411
  - Port a Data Register (PADR)
    411
  - Port B Data Direction Register (PBDDR)
    412
  - Port B Data Register (PBDR)
    412
  - Next Data Register a (NDRA)
    413
  - Next Data Register B (NDRB)
    415
  - Next Data Enable Register a (NDERA)
    417
  - Next Data Enable Register B (NDERB)
    418
  - TPC Output Control Register (TPCR)
    419
  - TPC Output Mode Register (TPMR)
    422
- Operation
  424
  - Output Timing
    425
  - Normal TPC Output
    426
  - Non-Overlapping TPC Output
    428
  - TPC Output Triggering by Input Capture
    430
- Usage Notes
  431
  - Operation of TPC Output Pins
    431
  - Note on Non-Overlapping Output
    431
Watchdog Timer

433
- Overview
  433
  - Features
    433
  - Block Diagram
    434
  - Pin Configuration
    434
  - Register Configuration
    435
- Register Descriptions
  436
- Operation
  443
- Interrupts
  447
- Usage Notes
  447

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