Refresh Controller Bus Timing - Hitachi H8/3048 Hardware Manual

21.4.2 Refresh Controller Bus Timing

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Refresh controller bus timing is shown as follows:
• DRAM bus timing
Figures 21-10 to 21-15 show the DRAM bus timing in each operating mode.
• PSRAM bus timing
Figures 21-16 and 21-17 show the pseudo-static RAM bus timing in each operating mode.
T
ø
t
AD
A to A
9 1
AS
t
RAD1
t
CS (RAS)
AS1
3
RD (CAS)
HWR (UW),
LWR ( LW
)
(read)
HWR (UW),
LWR ( LW
)
(write)
RFSH
D to D
15 0
(read)
D to D
15 0
(write)
Figure 21-10 DRAM Bus Timing (Read/Write): Three-State Access
T
1 2
t
AD
t
RAH
t
ASD
t
AS1
t
RAC
t
ASD
t
AA
t
WDS3
— 2WE Mode —
696
T
3
t
RAD3
t
SD
t
CAS
t
SD
t
CAC
t
WDH
t
RDS
t
RP
t
CRP
t
RDH