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Contention between RTCNT Write and Counter Clear: If a counter clear signal occurs in the
T
state of an RTCNT write cycle, clearing of the counter takes priority and the write is not
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performed. See figure 7-20.
ø
Address bus
Internal
write signal
Counter
clear signal
RTCNT
Figure 7-20 Contention between RTCNT Write and Clear
RTCNT write cycle by CPU
T
T
T
1
2
RTCNT address
N
178
3
H'00
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