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FLMCR:
.EQU
EBR1:
.EQU
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EBR2:
.EQU
TCSR:
.EQU
Set R0 value
;
START:
MOV.W
MOV.W
SUB.W
#RAMSTR is starting destination address to which program is transferred in RAM
;
;
Set #RAMSTR to even number
MOV.L
ADD.L
SUB.L
PRETST: CMP.B
BEQ
CMP.B
BCC
BTST
BNE
BRA
BC0:
BTST
BNE
PWADD1: INC.B
MOV.L
BRA
Execute prewrite
;
PREWRT: MOV.L
MOV.L
MOV.W
MOV.W
MOV.B
LOOPR0
DEC.W
BPL
MOV.W
PREW:
MOV.B
MOV.W
PREWRS: MOV.B
MOV.B
MOV.W
MOV.W
MOV.W
MOV.W
MOV.B
FFFF40
FFFF42
FFFF43
FFFFA8
#FFFF,
R6
R6,
R0
R1,
R1
#RAMSTR:32, ER2
#ERVADR:32, ER2
#START:32,
ER2
#10,
R1L
ERASES
#08,
R1L
BC0
R1L,
R0H
PREWRT
PWADD1
R1L,
R0L
PREWRT
R1L
@ER2+,
ER3
PRETST
@ER2+,
ER3
@ER2,
ER4
#g,
E5
#4140,
R5
R5L,
@FLMCR:8 ;
#1,
E5
LOOPR0
R6,
@EBR1:16 ;
#01,
R1H
#a,
E0
#00,
R5H
R5H,
@ER3
#A579,
E5
E5,
@TCSR:16 ;
E0,
E1
#4140,
R5
R5H,
@FLMCR:8 ;
602
;
Select blocks to be erased (R6: EBR1/EBR2)
R0: EBR1/EBR2
;
;
R1L: used to test R1-th bit in R0
Starting transfer destination address
;
#RAMSTR + #ERVADR → ER2
;
;
ER2: address of data area used in RAM
;
R1L = #10?
If finished checking all R0 bits, branch to ERASES
;
;
;
;
;
;
;
Test R1-th bit in R0
;
If R1-th bit in R0 is 1, branch to PREWRT
R1L + 1 → R1L
;
Dummy-increment ER2
;
;
ER3: prewrite starting address
ER4: top address of next block
;
;
Wait counter
;
Set V
E bit
PP
;
;
Set EBR (R6: EBR1/EBR2)
;
Prewrite-verify fail count
;
Set initial prewrite loop counter value
Write #00 data
;
;
;
Start watchdog timer
Set program loop counter
;
;
Set P bit
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