Hitachi H8/3048 Hardware Manual page 695

Table 21-15 Timing of On-Chip Supporting Modules
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Condition A: V
CC
V
SS
specifications), T
Condition C: V
CC
V
SS
specifications), T
Item
DMAC DREQ setup time
DREQ hold time
TEND delay time 1
TEND delay time 2
ITU Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
SCI Input clock
cycle
Input clock rise time
Input clock fall time
Input clock pulse width
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V
CC
= AV = 0 V, ø = 1 MHz to 8 MHz, T
SS
= –40°C to +85°C (wide-range specifications)
a
= 5.0 V ± 10%, AV = 5.0 V ± 10%, V
CC
= AV = 0 V, ø = 1 MHz to 16 MHz, T
SS
= –40°C to +85°C (wide-range specifications)
a
Symbol
t
DRQS
t
DRQH
t
TED1
t
TED2
t
TOCD
t
TICS
t
TCKS
Single edge t
TCKWH
Both edges t
TCKWL
Asynchronous t
SCYC
Synchronous t
SCYC
t
SCKr
t
SCKf
t
SCKW
= 2.7 V to AV
REF
= –20°C to +75°C (regular
a
= 4.5 V to AV
REF
= –20°C to +75°C (regular
a
Condition A Condition C
8 MHz 16 MHz
Min Max Min
40 — 30
10 — 10
— 100 —
— 100 —
— 100 —
50 — 50
50 — 50
1.5 — 1.5
2.5 — 2.5
4 — 4
6 — 6
— 1.5 —
— 1.5 —
0.4 0.6 0.4
687
,
CC
,
CC
Test
Max Unit Conditions
— ns Figure 21-30
—
50 Figure 21-28,
Figure 21-29
50
100 ns Figure 21-24
—
— Figure 21-25
— t
CYC
—
— t Figure 21-26
CYC
—
1.5
1.5
0.6 t
SCYC