Table of Contents
Advertisement
17.2 System Control Register (SYSCR)
www.DataSheet4U.com
Bit
SSBY
Initial value
Read/Write
R/W
Software standby
One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is
enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3,
System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized at the rising edge of the input at the
mode.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
7
6
5
STS2
STS1
0
0
0
R/W
R/W
Standby timer select 2 to 0
4
3
2
STS0
UE
NMIEG
0
1
0
R/W
R/W
R/W
NMI edge select
User bit enable
RES pin. It is not initialized in software standby
555
1
0
—
RAME
1
1
—
R/W
RAM enable
Enables or
disables
on-chip RAM
Reserved bit
(Initial value)
Advertisement
Table of Contents
