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RTMCSR—Refresh Timer Control/Status Register
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Bit
7
CMF
Initial value
0
Read/Write
R/(W)
*
Compare match flag
0 [Clearing condition]
1 [Setting condition]
Note:
Only 0 can be written, to clear the flag.
*
6
5
CMIE
CKS2
0
0
R/W
R/W
Clock select 2 to 0
Bit 5
CKS2
0
1
Compare match interrupt enable
0 The CMI interrupt requested by CMF is disabled
1 The CMI interrupt requested by CMF is enabled
Read CMF when CMF = 1, then write 0 in CMF
RTCNT = RTCOR
794
H'AD
4
3
2
CKS1
CKS0
—
0
0
1
R/W
R/W
—
Bit 4
Bit 3
CKS1
CKS0
Counter Clock Source
0
0
Clock input is disabled
1
ø/2
1
0
ø/8
1
ø/32
0
0
ø/128
1
ø/512
1
0
ø/2048
1
ø/4096
Refresh controller
1
0
—
—
1
1
—
—
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