Hitachi H8/3048 Hardware Manual page 757

DTCR0A—Data Transfer Control Register 0A
(cont)
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• Full address mode
Bit 7
DTE
Initial value 0
Read/Write R/W
Source address increment/decrement (bit 5)
Source address increment/decrement enable (bit 4)
Bit 5 Bit 4
SAID SAIDE Increment/Decrement Enable
0 0 MARA is held fixed
1 Incremented:
1 0 MARA is held fixed
1 Decremented:
Data transfer size
0 Byte-size transfer
1 Word-size transfer
Data transfer enable
0 Data transfer is disabled
1 Data transfer is enabled
6 5 4
DTSZ SAID SAIDE
0 0 0
R/W R/W R/W
Data transfer interrupt enable
If DTSZ = 0, MARA is incremented by 1 after each transfer
If DTSZ = 1, MARA is incremented by 2 after each transfer
If DTSZ = 0, MARA is decremented by 1 after each transfer
If DTSZ = 1, MARA is decremented by 2 after each transfer
750
H'27
3 2
DTIE DTS2A
0 0
R/W R/W
Data transfer select 0A
0 Normal mode
1 Block transfer mode
Data transfer select 2A and 1A
Set both bits to 1
0 Interrupt request by DTE bit is disabled
1 Interrupt request by DTE bit is enabled
DMAC0
1 0
DTS1A DTS0A
0 0
R/W R/W