Hitachi H8/3048 Hardware Manual page 397

Contention between General Register Read and Input Capture: If an input capture signal
occurs during the T
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See figure 10-66.
ø
Address bus
Internal read signal
Input capture signal
GR
Internal data bus
Figure 10-66 Contention between General Register Read and Input Capture
state of a general register read cycle, the value before input capture is read.
3
General register read cycle
T T
1 2
GR address
X
T
3
M
X
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