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M16C/62P Group (M16C/62P, M16C/62PT)
8.2 Bus Control
The following describes the signals needed for accessing external devices and the functionality of software wait.
8.2.1 Address Bus
The address bus consists of 20 lines, A0 to A19. The address bus width can be chosen to be 12, 16 or 20
bits by using the PM06 bit in the PM0 register and the PM11 bit in the PM1 register. Table 8.2 shows the
PM06 and PM11 bit set values and address bus widths.
Table 8.2 PM06 and PM11 Bits Set Value and Address Bus Width
(1)
Set Value
PM11=1
PM06=1
PM11=0
PM06=1
PM11=0
PM06=0
NOTES :
1. No values other than those shown above can be set.
When processor mode is changed from single-chip mode to memory extension mode, the address bus is
indeterminate until any external area is accessed.
8.2.2 Data Bus
When input on the BYTE pin is high(data bus is 8 bits wide), 8 lines D0 to D7 comprise the data bus; when
input on the BYTE pin is low(data bus is 16 bits wide), 16 lines D0 to D15 comprise the data bus.
Do not change the input level on the BYTE pin while in operation.
8.2.3 Chip Select Signal
The chip select (hereafter referred to as the CSi) signals are output from the CSi (i = 0 to 3) pins. These
pins can be chosen to function as I/O ports or as CS by using the CSi bit in the CSR register.
Figure 8.1 shows the CSR register.
During 1-Mbyte mode, the external area can be separated into up to 4 by the CSi signal which is output
______
from the CSi pin. During 4-Mbyte mode, CSi signal or bank number is output from the CSi pin. Refer to 9.
Memory space expansion function. Figure 8.2 shows the example of address bus and CSi signal
output in 1-Mbyte mode.
Chip Select Control Register
b7
b6
b5
NOTES :
1. Where the RDY signal is used in the area indicated by CSi (i = 0 to 3) or the multiplex bus is used, set the
CSiW bit to "0" (with wait state).
2. If the PM17 bit in the PM1 register is set to "1" (with wait state), set the CSiW bit to "0" (with wait state).
3. When the CSiW bit = 0 (with wait state), the number of wait states (interms of clock cycles) can be selected
using the CSEi1W to CSEi0W bits in the CSE register.
Figure 8.1 CSR Register
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
Pin Function
P3_4 to P3_7
P4_0 to P4_3
A12 to A15
P4_0 to P4_3
A12 to A15
A16 to A19
______
b4
b3
b2
b1
b0
Symbol
CSR
Bit Symbol
CS0
CS0 Output Enable Bit
CS1 Output Enable Bit
CS1
CS2
CS2 Output Enable Bit
CS3
CS3 Output Enable Bit
CS0W
CS0 Wait Bit
CS1W
CS1 Wait Bit
CS2W
CS2 Wait Bit
CS3W
CS3 Wait Bit
page 47
f o
3
6
4
Address Bus Width
12 bits
16 bits
20 bits
______
_____
Address
After Reset
0008h
00000001b
Bit Name
Function
0 : Chip select output disabled
(functions as I/O port)
1 : Chip select output enabled
0 : With wait state
1 : Without wait state
______
______
______
______
RW
RW
RW
RW
RW
RW
RW
(1, 2, 3)
RW
RW
8. Bus
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