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M16C/62P Group (M16C/62P, M16C/62PT)
(1) IICM2= 0 (ACK and NACK interrupts), CKPH= 0 (no clock delay)
SCLi
SDAi
(3) IICM2= 1 (UART transmit/receive interrupt), CKPH= 0
SCLi
SDAi
(4) IICM2= 1, CKPH= 1
SCLi
SDAi
i=0 to 2
This diagram applies to the case where the following condition is met.
• UiMR register CKDIR bit = 0 (Slave selected)
Figure 17.22 Transfer to UiRB Register and Interrupt Timing
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
D7
D6
D5
D4
D3
D7
D6
D5
D4
D3
D7
D6
D5
D4
D3
page 185
f o
3
6
4
D2
D1
D0
D8 (ACK, NACK)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
D2
D1
D0
D8 (ACK, NACK)
Receive interrupt
Transmit interrupt
(DMA1 request)
Transfer to UiRB register
D2
D1
D0
D8 (ACK, NACK)
17. Serial I/O
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