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M16C/62P Group (M16C/62P, M16C/62PT)
The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP
at the time of acceptance of an interrupt request, is even or odd. If the stack pointer
register and the PC are saved,16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure
12.7 shows the operation of the saving registers.
NOTES:
1. When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indi-
cated by the U flag. Otherwise, it is the ISP.
(1) SP contains even number
Address
[SP] – 5 (Odd)
[SP] – 4 (Even)
[SP] – 3(Odd)
[SP] – 2 (Even)
[SP] – 1(Odd)
[SP]
(2) SP contains odd number
Address
[SP] – 5 (Even)
[SP] – 4(Odd)
[SP] – 3 (Even)
[SP] – 2(Odd)
[SP] – 1 (Even)
[SP]
(Odd)
PCH : 4 high-order bits of PC
PCM : 8 middle-order bits of PC
PCL
: 8 low-order bits of PC
NOTES :
1. [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 12.7 Operation of Saving Register
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
Stack
PCL
PCM
FLGL
FLGH
(Even)
Stack
PCL
PCM
FLGL
FLGH
f o
3
6
4
page 100
Sequence in which order
registers are saved
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
PCH
Finished saving registers
in two operations.
Sequence in which order
registers are saved
(3)
(4)
Saved, 8 bits at a time
(1)
PCH
(2)
Finished saving registers
in four operations.
FLGH : 4 high-order bits of FLG
FLGL : 8 low-order bits of FLG
12. Interrupt
(1)
,
(1)
is even, the FLG
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